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A Latch has three input terminals (a_0, a_1, and b), and two output terminals (c_0 and c_1). It waits for a signal on exactly one of the a_i inputs and a signal on the b input. In contrast to a Sequencer, the environment must guarantee mutual exclusion of the a_i-inputs. Having received input signals on a_i (i=0 or i=1) and b, it produces a signal on output terminal c_i.

Rephrasing: Both the a and the c wire pair can be viewed as encoding one bit of data by a One-Hot code. When a bit is sent to the Latch via an a input, it stores (latches) this bit until b is received. Reception of b reproduces the bit via the corresponding c ouput.

Each pair of terminals (a_i, c_i) can be viewed as one passive 2-phase handshake port. A Latch synchronizes a handshake on one of its handshake ports with the b input.


Schematic diagram for a Latch:


XDI state graph for a Latch:


Specification in XDI model.


Specification in Verdect:

define JOIN2X1( a0?, a1?, b?, c0!, c1! ) =
       pref *[ (a0? || b?); c0!
             | (a1? || b?); c1!
Also available through this link

DI Algebra

Specification in DI Algebra:

L = [ a0? -> [ a1? -> _|_ # b? -> c0!; L ]
    # a1? -> [ a0? -> _|_ # b? -> c1!; L ]
Also available through this link


XDI Report..

The roles of subscripts 0 and 1 can be interchanged (on a and c simultaneously):
L(a_0, a_1, b; c_0, c_1) = L(a_1, a_0, b; c_1, c_0)


DI Decompositions

  1. A Latch is implemented by a Sequencer (not equ).
  2. It can also be implemented with a Decision-Wait by properly terminating one unneeded input and two unneeded outputs (e.g., with a Merge or Join). Similar implementations exist using a properly terminated Partial Decision-Wait or a 2-3-Complementer.
  3. A Latch can be implemented with a Resettable Join RJ(a_0, b, a_1; c_0, c_1) (not equ).
  4. A Latch can be implemented with a Non-Receptive Mixer and a Join (equ):


Using Boolean Gates

No information available

Using Transistors

No information available


The Latch can be generalized in several ways. It can be generalized to a k-Latch, which latches a choice between k inputs. A Latch is a 2-Latch.

It can be further generalized to an mxn-Decision-Wait, which awaits two choices, one between m inputs and the other between n inputs, and reports the combination as a choice among mn outputs. a Latch is a 2x1-Decision-Wait.


In terms of [Ebergen89, p. 88], the Latch is a CAL component.

The Latch is sometimes also referred to as Decision-Wait ([Lucassen94]) or 2x1-Join.

Conjecture: A Latch cannot be implemented with only Forks, Joins, Merges, Toggles, and I-Wires.


[Ebergen89, p. 88]

Last modified at Fri Nov 20 10:11:40 1998
Encyclopaedia of Delay-Insensitive Systems
Copyright © 1995-1998 Tom Verhoeff / Tom.Verhoeff@acm.org