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kLatch
Informal
A kLatch (k>0) has k+1 input
terminals a_i (0<=i<k) and b,
and k output terminals c_i (0<=i<k).
It waits for a signal on exactly one of the a inputs and
a signal on the b input.
In contrast to
a kSequencer,
the environment must guarantee mutual exclusion of the ainputs.
Having received input signals on a_i (0<=i<k)
and b, it produces a signal on output terminal c_i.
Rephrasing: Both the a and the c wire pair can be viewed
as encoding a value by a OneHot code.
When the value is sent to the kLatch via an
a input, it stores (latches) this value until b is received.
Reception of b reproduces the value via the corresponding c
ouput.
Schematic diagram
for a kLatch:
[ZoomFIG]
We provide the XDI specification for the
a 3Latch:
Specification in XDI model.
(Not available for general k.)
Parameterized definitions are not possible in VERDECT, but this sketch gives
the general idea:
Specification in Verdect:
define L( a0?, ..., a(k1)?, b?, c0!, ..., c(k1)! ) =
pref *[ (a0?  b?); c0!
 ...
 (a(k1)?  b?); c(k1)!
]
end
Also available through this link
The specification of the 3Latch is as
follows: Specification in Verdect:
define L( a0?, a1?, a2?, b?, c0!, c1!, c2! ) =
pref *[ (a0?  b?); c0!
 (a1?  b?); c1!
 (a2?  b?); c2!
]
end
Also available through this link.
Parameterized definitions are not possible in DI Algebra,
but this sketch gives the general idea:
Specification in DI Algebra:
I = { a0?, .. , a(k1)?, b? }
O = { c0?, .. , c(k1)! }
L(k,k) = [ (,i: 0<=i < k: ai? > L(i,k),
b? > M(k,k)
]
L(i,k) = [ b? > M(i,k), else > CHAOS ], for 0<=i M(i,k), b? > CHAOS]
M(i,k) = ci!;L(k,k)
Also available through this link
We provide the specification for the
3Latch:
Specification in DI Algebra.
The XDI Report for the
3Latch.
The roles of subscripts i can be permuted
(on a_i and c_i simultaneously).
The kLatch satisfies Rules Y' and Z^out, but not
Z^inp (choice between a inputs).
DI Decompositions

A 1Latch is
a Join.

A 2Latch is
a Latch.

A kLatch is implemented by
a Sequencer (not equ).

A (m+n)Latch can be implemented with
a knrmixer and
a (n+1)Latch (equ):
[ZoomFIG]
Using Boolean Gates
No information available
Using Transistors
No information available
The kLatch can be generalized to
an mxnDecisionWait,
which awaits two choices,
one between m inputs and the other between n inputs,
and reports the combination as a choice among mn outputs.
A kLatch is a
kx1DecisionWait.
In terms of [Ebergen89, p. 88],
the kLatch is a CAL component.
The kLatch is sometimes also referred
to as DecisionWait ([Lucassen94])
or kx1Join.
[Ebergen89, p. 88]
[Lucassen94]
Last modified at Fri Nov 20 10:11:40 1998
Encyclopaedia of DelayInsensitive Systems
Copyright © 19951998
Tom Verhoeff /
Tom.Verhoeff@acm.org