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Partial Decision-Wait



A Partial Decision-Wait has four input terminals (a_0, a_1, b_0, and b_1), and three output terminals (c_00, c_01, and c_10). It waits for a signal on one of the a inputs and a signal on one of the b inputs. The environment has to guarantee mutual exclusion on the a-inputs and also the b-inputs. Furthmore, the combination a_1 and b_1 is not allowed. Having received input signals on a_i (i=0 or i=1) and b_j (j=0 or j=1) with i+j<2, it produces a signal on output terminal c_ij.

Rephrasing: A Partial Decision-Wait receives two bits of data (not both 1) in a Double-Rail code via the a and b inputs and converts them to a three-wire One-Hot code via the c outputs.

A Partial Decision-Wait can also be viewed as a restricted kind of Resettable Join, where a_0 and b_0 are the inputs to be joined into c_00 and a_1 and b_1 are the resets with acknowledges c_10 and c_01 respectively. However, it can only be reset via a_1 when partially set by b_0, or via b_1 when partially set by a_0. Also see Implementations.


Schematic diagram for a Partial Decision-Wait:


XDI state graph for a Partial Decision-Wait:


Specification in XDI model.


Specification in Verdect:

define PDW( a0?, a1?, b0?, b1?, c00!, c01!, c10! ) =
       pref *[ (a0? || b0?); c00!
             | (a0? || b1?); c01!
             | (a1? || b0?); c10!
Also available through this link

DI Algebra

Specification in DI Algebra:

PDW = [ a0? -> [ a1? -> _|_
               # b0? -> [ b1? -> _|_ # skip -> c00!; PDW ]
               # b1? -> [ b0? -> _|_ # skip -> c01!; PDW ]
      # a1? -> [ a0? -> _|_
               # b0? -> [ b1? -> _|_ # skip -> c10!; PDW ]
               # b1? -> _|_
      # b0? -> [ b1? -> _|_
               # a0? -> [ a1? -> _|_ # skip -> c00!; PDW ]
               # a1? -> [ a0? -> _|_ # skip -> c10!; PDW ]
      # b1? -> [ b0? -> _|_
               # a0? -> [ a1? -> _|_ # skip -> c01!; PDW ]
               # a1? -> _|_
Also available through this link


XDI Report.

The roles of the a and b inputs can be interchanged, provided the c outputs are permuted accordingly:
PDW(a_0, a_1, b_0, b_1; c_00, c_01, c_10) = PDW(b_0, b_1, a_0, a_1; c_00, c_10, c_01)


DI Decompositions

  1. A Partial Decision-Wait can be implemented with a Decision-Wait by terminating the c_11 output with a 0-Sink (equ) or Sink (not equ). It is also possible to combine the c_11 output with any of the other outputs through a Merge (not equ).
  2. A Partial Decision-Wait can be implemented with a 2-3-Complementer and a Merge (not equ):

  3. A Partial Decision-Wait can be implemented with a Resettable Join and a Non-Receptive Mixer (not equ):


Using Boolean Gates

No information available

Using Transistors

No information available


The Partial Decision-Wait can be generalized by any generalization of a Decision-Wait together with a set of outputs to be avoided (these outputs can be thought of as terminated with a 0-Sink).


Conjecture: A Partial Decision-Wait cannot be implemented with only Fork, Join, Merge, Latch (or even Sequencer), and I-Wire.


Last modified at Fri Nov 20 10:11:40 1998
Encyclopaedia of Delay-Insensitive Systems
Copyright © 1995-1998 Tom Verhoeff / Tom.Verhoeff@acm.org