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I-Wire

Specifications

Informal

An I-Wire has one input terminal and one output terminal. It starts by producing a signal on the output terminal, after which it behaves like a Wire, i.e., it copies input signals to output signals. Output and input signals alternate.

The name ` I-Wire' derives from `Initialized Wire', a Wire with an initial signal on it.

XDI

Schematic diagram for an I-Wire:

[Zoom|FIG]

XDI state graph for an I-Wire:

[Zoom|FIG]

Specification in XDI model:

(AND/IF_1.0
  (NFA
    (NAME I-Wire)
    (SYMBOLS 
      (a INPUT) (b OUTPUT)
    )

    (STATES
      (0 INITIAL TRANSIENT)
      (1 BOX)
    )
    (TRANSITIONS
      (0 1 b)
      (1 0 a)
    )
  )
)
Also available through this link

Verdect

Specification in Verdect:


define IWIRE( a?, b! ) =
       pref *[ b!; a? ]
end
Also available through this link

DI Algebra

Specification in DI Algebra:


I = b!; a?; I
Also available through this link

Properties

XDI Report.

I(a; b) / b = W(a; b)

The I-Wire is active.

Implementations

DI Decompositions

  1. An I-Wire can be implemented with an Active Source and a Merge:


    [Zoom|FIG]

    The Ludwig verification script of this implementation.

Using Boolean Gates

No information available

Using Transistors

No information available

Generalizations

No information available

Miscellaneous

In Section 2.2.1 of [Ebergen89, p. 29] the I-Wire is referred to as a IWIRE component.

(Something should be added about how to realize initialization "electronically".)

References

[Ebergen89, p. 29]


Last modified at Fri Nov 20 10:11:39 1998
Encyclopaedia of Delay-Insensitive Systems
Copyright © 1995-1998 Tom Verhoeff / Tom.Verhoeff@acm.org