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A (non-arbitrating, blocking) Call has three input terminals (a0, a1, b) and three output terminals (c, d0, d1). A signal appearing on either of the a_i terminals will cause a signal to be produced at terminal c. The combination of a signal at terminal a_i and terminal b will cause a signal to be produced at terminal d_i. It does not matter which of the two input signals arrives first.

The environment of a Call must guarantee mutual exclusion of the signals on a0 and a1. The a_i and c signals alternate, the a_i and d_i signals alternate, and the b and d_i signals alternate.


Schematic diagram for a Call:


XDI state graph for a Call:


Specification in XDI model.


Specification in Verdect:

define CALL( a0?, d0!, a1?, d1!, c!, b? ) =
       pref *[ (a0? | a1?); c! ]
    || pref *[ (a0? || b?); d0!
             | (a1? || b?); d1!
Also available through this link

DI Algebra

Specification in DI Algebra:

NAME = Call
I = { a0, a1, b }
O = { d0, d1, c }

CALL = [a0? -> c!; C0, a1? -> c!; C1]
C0   = [b? -> d0!; CALL, a0? -> CHAOS, a1? -> CHAOS]
C1   = [b? -> d1!; CALL, a0? -> CHAOS, a1? -> CHAOS]
Also available through this link


XDI Report.

The roles of subscripts 0 and 1 can be interchanged:
CALL(a0, d0, a1, d1, c, b) = CALL(a1, d1, a0, d0, c, b)


DI Decompositions

  1. A Call can be implemented with two Forks, a Merge and a Latch (equ):


    The AND/IF network description of this implementation.
    The Ludwig verification script of this implementation.

Using Boolean Gates

No information available

Using Transistors

No information available


The Call can be generalized to a k-Call, which merges and latches k (mutually exlusive) inputs. A Call is a 2-Call.


In [Ornstein67, p. 345], a Call is referred to as `Call Unit'.

In [Dickson74, p. 46], a Call does not appear as such, but it is mentioned that a CALL element (what we refer to as Decision Call) may be used as a `Simple Call'. It is not clear from the informal description given there when new input signals can be offered. In particular, it is not clear whether a new input signal on b must await output signal c, that is, whether b is enabled in state 9.


[Dickson74, p. 46]
[Ornstein67, p. 345]

Last modified at Fri Nov 20 10:11:39 1998
Encyclopaedia of Delay-Insensitive Systems
Copyright © 1995-1998 Tom Verhoeff / Tom.Verhoeff@acm.org