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# RGd1 Arbiter

## Specifications

### Informal

An RGd1 Arbiter has three input terminals (r_0, d_0, r_1, and d_1) and two output terminals (g_0 and g_1). For each i in {0,1}, signaling starts with r_i followed by a repetition of g_i then concurrently d and r_i. The intervals from g_0 to d and from g_1 to d are mutually exclusive (do not overlap).

RGD stands for Request (r_i), Grant (g_i), and Done (d).

When An RGd1 Arbiter receives two requests, it will grant exactly one of them (and delay the other). The specification leaves the choice open. Often there is a fairness requirement on this choice: if a choice situation arises `infinitely often' then both outputs are chosen `infinitely often'.

The RGd1 Arbiter only has a single done input, in contrast to the more common variant, the RGD Arbiter that has two done inputs, one for each requesting party.

### XDI

Schematic diagram for an RGd1 Arbiter:

[Zoom|FIG]

XDI state graph for an RGd1 Arbiter:

[Zoom|FIG]

Specification in XDI model.

### Verdect

No information available

### DI Algebra

Specification in DI Algebra:

```NAME = "RGD 1-arbiter"
I   = { r0?, r1?, d? }
O   = { g0!, g1! }
RGD = [ r0? -> g0! ; d?; RGD,
r1? -> g1! ; d?; RGD,
d? -> CHAOS
]

```
Also available through this link

## Properties

XDI Report.

The subscripts 0 and 1 can be interchanged systematically.

An RGd1 Arbiter is not output deterministic. The output nondeterminism is dynamic.

## Implementations

### Using Boolean Gates

No information available

### Using Transistors

No information available

## Generalizations

No information available

## Miscellaneous

No information available

## References

###### Last modified at Fri Nov 20 10:11:41 1998
Encyclopaedia of Delay-Insensitive Systems
Copyright © 1995-1998 Tom Verhoeff / Tom.Verhoeff@acm.org